Difference between revisions of "random access memory/timing"
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** It usually is T1 (1 clock cycle) or T2 (2 clock cycles). | ** It usually is T1 (1 clock cycle) or T2 (2 clock cycles). | ||
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==Source== | ==Source== | ||
* '''2011-05-17''' [https://hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings] | * '''2011-05-17''' [https://hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings] | ||
==Reference== | ==Reference== | ||
* Wikipedia: {{l/wp|Memory timings}} | * Wikipedia: {{l/wp|Memory timings}} |
Revision as of 17:52, 28 June 2021
In general, lower numbers are better (the only exception is the speed). RAM should work in a device as long as the device's required numbers are not lower than those for the RAM.
I think the format is:
- <tech>-<internal clock speed> <CAS>-<tRCD>-<tRP>-<tRAS>[-<CMD>]
- example: PC3-10600S-09-10-F2
- tech = PC3
- speed = 10600 (S = ?)
- CAS = 09
- tRCD = 10
- tRP = F2(?)
- example: PC3-10600S-09-10-F2
...but I haven't been able to confirm all of this.
Terms
- CAS = Column Address Strobe latency, aka CL
- CASn or CLn means the memory controller must wait n clock cycles until data is delivered after a request is made
- This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it.
- tRCD = RAS-to-CAS Delay = the time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix
- tRP = RAS Precharge = the time it takes between disabling the access to a line of data and the beginning of the access to another line of data
- tRAS = Active to Precharge Delay = how long the memory has to wait until the next access to the memory can be initiated
- CMD = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory
- Sometimes this value is not shown.
- It usually is T1 (1 clock cycle) or T2 (2 clock cycles).
Source
- 2011-05-17 Understanding RAM Timings
Reference
- Wikipedia: Memory timings