Difference between revisions of "random access memory/timing"

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(more info from Wikipedia; changed variable formatting to use subscript)
 
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I ''think'' the format is:
 
I ''think'' the format is:
−
* {{arg|tech}}-{{arg|internal clock speed}} {{arg|CAS}}-{{arg|tRCD}}-{{arg|tRP}}-{{arg|tRAS}}[-{{arg|CMD}}]
+
* {{arg|tech}}-{{arg|internal clock speed}} {{arg|CAS}}-{{arg|T<sub>RCD</sub>}}-{{arg|T<sub>RP</sub>}}-{{arg|T<sub>RAS</sub>}}[-{{arg|CMD}}]
 
** '''example''': PC3-10600S-09-10-F2
 
** '''example''': PC3-10600S-09-10-F2
 
*** tech = PC3
 
*** tech = PC3
 
*** speed = 10600 (S = ?)
 
*** speed = 10600 (S = ?)
 
*** CAS = 09
 
*** CAS = 09
−
*** tRCD = 10
+
*** T<sub>RCD</sub> = 10
−
*** tRP = F2(?)
+
*** T<sub>RP</sub> = F2(?)
 
...but I haven't been able to confirm all of this.
 
...but I haven't been able to confirm all of this.
 
==Terms==
 
==Terms==
−
* '''CAS''' = Column Address Strobe latency, aka CL
+
* '''CAS''' or '''CL''' = Column Address Strobe latency
 
** CAS''n'' or CL''n'' means the memory controller must wait ''n'' clock cycles until data is delivered after a request is made
 
** CAS''n'' or CL''n'' means the memory controller must wait ''n'' clock cycles until data is delivered after a request is made
 
** This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it.
 
** This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it.
−
* '''tRCD''' = RAS-to-CAS Delay = the time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix
+
** This terminology is a holdover from asynchronous DRAM.
−
* '''tRP''' = RAS Precharge =  the time it takes between disabling the access to a line of data and the beginning of the access to another line of data
+
* '''RAS''' = Row Address Strobe
−
* '''tRAS''' = Active to Precharge Delay = how long the memory has to wait until the next access to the memory can be initiated
+
** This terminology is a holdover from asynchronous DRAM.
 +
* '''T<sub>RCD</sub>''' = RAS-to-CAS Delay = the time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix; the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is T<sub>RCD</sub> + CAS.
 +
* '''T<sub>RP</sub>''' = RAS Precharge =  the time it takes between disabling the access to a line of data and the beginning of the access to another line of data; the minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is T<sub>RP</sub> + T<sub>RCD</sub> + CL.
 +
* '''T<sub>RAS</sub>''' = Active to Precharge Delay = how long the memory has to wait until the next access to the memory can be initiated; the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with T<sub>RCD</sub>. In SDRAM modules, it is simply T<sub>RCD</sub> + CL. Otherwise, approximately equal to T<sub>RCD</sub> + 2×CL.
 
* '''CMD''' = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory
 
* '''CMD''' = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory
 
** Sometimes this value is not shown.
 
** Sometimes this value is not shown.
 
** It usually is T1 (1 clock cycle) or T2 (2 clock cycles).
 
** It usually is T1 (1 clock cycle) or T2 (2 clock cycles).
  
−
Usually, you have two options: to configure your PC to use the memory standard timings, usually by setting memory configuration to “Auto” on the motherboard setup; or to manually configure your PC to use lower memory timings, which may increase the performance of your system. Notice that not all motherboards allow you to change the memory timings. Also, some motherboards may not be able to run at very low timings, and they may configure your memory module to run at a higher timing setting because of this.
 
 
==Source==
 
==Source==
 
* '''2011-05-17''' [https://hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings]
 
* '''2011-05-17''' [https://hardwaresecrets.com/understanding-ram-timings/ Understanding RAM Timings]
 
==Reference==
 
==Reference==
 
* Wikipedia: {{l/wp|Memory timings}}
 
* Wikipedia: {{l/wp|Memory timings}}

Latest revision as of 12:58, 29 June 2021

In general, lower numbers are better (the only exception is the speed). RAM should work in a device as long as the device's required numbers are not lower than those for the RAM.

I think the format is:

  • <tech>-<internal clock speed> <CAS>-<TRCD>-<TRP>-<TRAS>[-<CMD>]
    • example: PC3-10600S-09-10-F2
      • tech = PC3
      • speed = 10600 (S = ?)
      • CAS = 09
      • TRCD = 10
      • TRP = F2(?)

...but I haven't been able to confirm all of this.

Terms

  • CAS or CL = Column Address Strobe latency
    • CASn or CLn means the memory controller must wait n clock cycles until data is delivered after a request is made
    • This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it.
    • This terminology is a holdover from asynchronous DRAM.
  • RAS = Row Address Strobe
    • This terminology is a holdover from asynchronous DRAM.
  • TRCD = RAS-to-CAS Delay = the time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix; the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CAS.
  • TRP = RAS Precharge = the time it takes between disabling the access to a line of data and the beginning of the access to another line of data; the minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
  • TRAS = Active to Precharge Delay = how long the memory has to wait until the next access to the memory can be initiated; the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL.
  • CMD = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory
    • Sometimes this value is not shown.
    • It usually is T1 (1 clock cycle) or T2 (2 clock cycles).

Source

Reference

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