Difference between revisions of "random access memory/timing"
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(more info from Wikipedia; changed variable formatting to use subscript) |
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I ''think'' the format is: | I ''think'' the format is: | ||
| − | * {{arg|tech}}-{{arg|internal clock speed}} {{arg|CAS}}-{{arg| | + | * {{arg|tech}}-{{arg|internal clock speed}} {{arg|CAS}}-{{arg|T<sub>RCD</sub>}}-{{arg|T<sub>RP</sub>}}-{{arg|T<sub>RAS</sub>}}[-{{arg|CMD}}] |
** '''example''': PC3-10600S-09-10-F2 | ** '''example''': PC3-10600S-09-10-F2 | ||
*** tech = PC3 | *** tech = PC3 | ||
*** speed = 10600 (S = ?) | *** speed = 10600 (S = ?) | ||
*** CAS = 09 | *** CAS = 09 | ||
| − | *** | + | *** T<sub>RCD</sub> = 10 |
| − | *** | + | *** T<sub>RP</sub> = F2(?) |
...but I haven't been able to confirm all of this. | ...but I haven't been able to confirm all of this. | ||
==Terms== | ==Terms== | ||
| − | * '''CAS''' = Column Address Strobe latency | + | * '''CAS''' or '''CL''' = Column Address Strobe latency |
** CAS''n'' or CL''n'' means the memory controller must wait ''n'' clock cycles until data is delivered after a request is made | ** CAS''n'' or CL''n'' means the memory controller must wait ''n'' clock cycles until data is delivered after a request is made | ||
** This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it. | ** This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it. | ||
| − | * ''' | + | ** This terminology is a holdover from asynchronous DRAM. |
| − | * ''' | + | * '''RAS''' = Row Address Strobe |
| − | * ''' | + | ** This terminology is a holdover from asynchronous DRAM. |
| + | * '''T<sub>RCD</sub>''' = RAS-to-CAS Delay = the time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix; the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is T<sub>RCD</sub> + CAS. | ||
| + | * '''T<sub>RP</sub>''' = RAS Precharge = the time it takes between disabling the access to a line of data and the beginning of the access to another line of data; the minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is T<sub>RP</sub> + T<sub>RCD</sub> + CL. | ||
| + | * '''T<sub>RAS</sub>''' = Active to Precharge Delay = how long the memory has to wait until the next access to the memory can be initiated; the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with T<sub>RCD</sub>. In SDRAM modules, it is simply T<sub>RCD</sub> + CL. Otherwise, approximately equal to T<sub>RCD</sub> + 2×CL. | ||
* '''CMD''' = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory | * '''CMD''' = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory | ||
** Sometimes this value is not shown. | ** Sometimes this value is not shown. | ||
Latest revision as of 12:58, 29 June 2021
In general, lower numbers are better (the only exception is the speed). RAM should work in a device as long as the device's required numbers are not lower than those for the RAM.
I think the format is:
- <tech>-<internal clock speed> <CAS>-<TRCD>-<TRP>-<TRAS>[-<CMD>]
- example: PC3-10600S-09-10-F2
- tech = PC3
- speed = 10600 (S = ?)
- CAS = 09
- TRCD = 10
- TRP = F2(?)
- example: PC3-10600S-09-10-F2
...but I haven't been able to confirm all of this.
Terms
- CAS or CL = Column Address Strobe latency
- CASn or CLn means the memory controller must wait n clock cycles until data is delivered after a request is made
- This is the time it takes between (a) the processor asking for some data from the memory and (b) receiving it.
- This terminology is a holdover from asynchronous DRAM.
- RAS = Row Address Strobe
- This terminology is a holdover from asynchronous DRAM.
- TRCD = RAS-to-CAS Delay = the time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix; the minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CAS.
- TRP = RAS Precharge = the time it takes between disabling the access to a line of data and the beginning of the access to another line of data; the minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
- TRAS = Active to Precharge Delay = how long the memory has to wait until the next access to the memory can be initiated; the minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL.
- CMD = Command Rate = the number of clock cycles it takes between the memory chip having been activated and when the first command may be sent to the memory
- Sometimes this value is not shown.
- It usually is T1 (1 clock cycle) or T2 (2 clock cycles).
Source
- 2011-05-17 Understanding RAM Timings
Reference
- Wikipedia: Memory timings